> This was discussed in > > http://www.eda-stds.org/sv-bc/hm/5602.html Indeed; but unfortunately that interesting discussion did not give rise to any clarification of the LRM text, and (at least for me) left a number of questions at best partly answered - as I tried to express in http://www.eda-stds.org/sv-bc/hm/5608.html It is entirely possible that I'm being irremediably stupid about this; but, even if I am, it would perhaps be a good idea for the LRM to do a little more to help the slow learners like me. The fact that tools still somewhat disagree about this suggests that I may not be alone in my uncertainty. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Wed Jul 11 12:33:31 2007
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