RE: [sv-bc] uwire & wire -vs- reg

From: Steven Sharp <sharp_at_.....>
Date: Tue Jul 10 2007 - 11:24:29 PDT
>From: "Rich, Dave" <Dave_Rich@mentor.com>

>Cliff,
>
>The 'net' kind is essentially a builtin resoltion function that has no
>stored value (trireg being an exception). I believe that going forward
>in SV, you should always recommend using variables for all signals
>except in cases where multiple drivers are anticipated.

This has the potential to seriously impact simulation performance,
depending on the details of the implementation.  Port-collapsing
of nets has major performance advantages.

Steven Sharp
sharp@cadence.com


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Received on Tue Jul 10 11:24:46 2007

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