Cliff's votes: See attached document for explanations. SVDB 1119 ___Yes _X_No http://www.eda.org/svdb/bug_view_page.php?bug_id=1119 I have no strong objections to the proposal and added example. I just want to hear the EDA vendors on the committee say that their simulators behave this way or will behave this way. SVDB 1233 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1233 SVDB 1280 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1280 SVDB 1341 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1341 SVDB 1351 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1351 SVDB 1462 ___Yes _X_No http://www.eda.org/svdb/bug_view_page.php?bug_id=1462 does this take into account the enhancement to allow timeunit 1ns / 1ns; ?? SVDB 1625 ___Yes _X_No http://www.eda.org/svdb/bug_view_page.php?bug_id=1625 NOTE: Brad proposes that this is no longer as issue and should be resolved with no action required. Why is this no longer an issue? SVDB 1814 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1814 SVDB 1899 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1899 ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification Training -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sun Jul 8 21:15:18 2007
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