Re: [sv-bc] Case Statement Enhancement Proposal Idea

>In Stu's words, GOTCHA!

No, in Verilog, the width of a context-determined operator, such as <<,
does not depend solely on the width of its immediate operands. In the
following assignment

    always_comb y = en << a;

the shifter is as wide as the max of the widths of y and en.

Try this Verilog-1995 example in any simulator

module test;
reg [7:0] y;
initial begin
  y = 1'b1 << 6;
  $displayb(y);
end
endmodule


Or try this one

module test;
reg [7:0] y;
reg [19999:0] t;
initial begin
  t = 1'b1 << 10006 >> 10000;
  y = t;
  $displayb(y);
end
endmodule

-- Brad
    

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Bresticker, Shalom
Sent: Sunday, July 08, 2007 6:23 AM
To: Arturo Salz; sv-bc@eda.org
Subject: RE: [sv-bc] Case Statement Enhancement Proposal Idea

Actually not.

en is only 1 bit wide, and thus so is 'en << a'. 

In Stu's words, GOTCHA!

Shalom


>   always_comb y = en << a;
> 
> All these idioms are equivalent.

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