Re: [sv-bc] Case Statement Enhancement Proposal Idea

Hi, Brad -

At 06:06 PM 7/4/2007, Brad Pierce wrote:
>Cliff,
>
> >with the unique keyword, this still simulates like a 2-to-4 decoder and
>issues
> >a run-time warning whenever en=0 and the always_comb block is executed.
>
> >It also optimizes away the en-input to give the wrong logic when
>synthesized.
>
>It may not be the logic you wished for, but it's hardly "the wrong
>logic".  It's GIGO logic, hence the run-time warning from the simulator.

Better explanation. Thanks.

The point is, you can simulate one thing and synthesize something 
else and you currently only get a warning. You might catch this with 
formal tools (check for equivalence, not consistency) and you would 
hopefully catch it in gate-sims, but in both cases, the problem is 
discovered later than it should be (if it is caught at all).

Full_case parallel_case never gave simulation warnings. Now that we 
have unique and priority, we at least get warnings (these were errors 
until Accellera SV 3.1a when they turned into warnings). But the 
better solution is to avoid the problem altogether. The embedded 
case-initial statement fixes common coding bugs and helps to avoid 
inferred latches that are not fixed by case-default or the full_case 
directive. Once I have an embedded case-initial statement, I don't 
anticipate using priority case ever again (but I may use unique case 
almost all the time).

Regards - Cliff

>The LRM says --
>
>"If the case is qualified as priority or unique, the simulator shall
>issue a warning message if no case item matches. These warnings can be
>issued at either compile time or run time, as soon as it is possible to
>determine the illegal condition.
>
>"NOTE-By specifying unique or priority, it is not necessary to code a
>default case to trap unexpected case values."
>
>[ In reply to http://www.eda-stds.org/sv-bc/hm/6190.html . ]
>
>-- Brad
>
>
>--
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Cliff Cummings - Sunburst Design, Inc.
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