Re: [sv-bc] uwire & wire -vs- reg

>And it is just fodder for the passionate VHDL coders who are looking
>for more reasons to block the use of Verilog at their companies. 

I don't think it's a goal of this technical standardization effort to
increase the market share of Verilog/SystemVerilog vs. VHDL.

[ In reply to http://www.eda-stds.org/sv-bc/hm/6185.html .]

-- Brad


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