RE: [sv-bc] negative delays

I saw a note on Primetime explaining how a negative net delay could
occur.

The note gave a number of cases.

For example, suppose the transition point of the destination gate is far
from that of the driving gate. Then the transition at the destination
can be triggered even though the source has not yet reached its
transition point.

Shalom

> -----Original Message-----
> From: Steven Sharp [mailto:sharp@cadence.com]
> Sent: Sunday, June 24, 2007 11:53 PM
> To: sv-bc@eda.org; Bresticker, Shalom
> Subject: Re: [sv-bc] negative delays
> 
> I am not an expert on timing, but...
> 
> An actual negative interconnect delay could not represent physical
> reality (assuming causality holds in the universe).  However, I
> could imagine a situation where a nominal positive interconnect
> delay had been lumped into the output delay of a device, and then
> a negative interconnect delay was used to represent that the actual
> interconnect delay was less than that nominal value, i.e. to cancel
> out some of the excessive interconnect delay that had been lumped
> into the device output delay.
> 
> The only practical way I can see to simulate this would also be
> if there was an output delay, and the negative interconnect delay
> could be implemented by reducing the output delay to a smaller but
> still positive value.  But a tool would have to have been designed
> to expect and implement this situation.
> 
> Steven Sharp
> sharp@cadence.com

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