[sv-bc] RE: [sv-ec] Formatting strings using %b ???

Jonathan,

The string data type is an unpacked aggregate. To convert to an integral
type requires a cast, and under any other circumstance, this should be
an error. However, an argument to a system task does not create an
assignment context, so we are free to choose the behavior we want.

I do think it's preferable to display the ASCII representation in the
radix specified. We should not allow reals.

Dave


> -----Original Message-----
> From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org]
On
> Behalf Of Jonathan Bromley
> Sent: Thursday, June 21, 2007 11:38 PM
> To: sv-bc@server.eda-stds.org; sv-ec@server.eda-stds.org
> Subject: [sv-ec] Formatting strings using %b ???
> 
> hi SV-BC,
> 
> Copied to EC because it may relate to the current discussion of Mantis
> 1789.
> 
> I recently saw divergent behaviour between two simulators when I
> mistakenly
> tried to display a SystemVerilog string variable using
> 
>   string S = "something";
>   $display("%b", S);
> 
> One simulator evidently cast the string to a vector of bits
(traditional
> Verilog
> string) and displayed that in binary.  The other displayed the string
as a
> string.
> Clearly, a third possibility would be to throw an error.
> 
> It's not completely clear to me which behaviour is correct.  Is a
string
> an
> unpacked, or a packed array of bytes (characters)? Or neither?
> 
> Thanks
> --
> Jonathan Bromley
> 
> 
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