RE: [sv-bc] Request from the SV-CC

Chas-

Is the requirement that there must be a mapping file, or can
implementations auto-generate the names just like they do for unnamed
blocks?

Also: must it be a file, or could it be any other mechanism, like a
command line switch?

Dave


> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Charlie Dawson
> Sent: Thursday, June 21, 2007 8:01 AM
> To: SV-BC
> Cc: Karen Pieper
> Subject: [sv-bc] Request from the SV-CC
> 
> Hi SV-BC,
> 
> The SV-CC has directed me, as chair of SV-CC, to request that the
SV-BC
> consider adding language to the LRM requiring implementations to have
a
> mapping file which will bind names to $units objects.
> 
> Please let me know if this request needs further explanation.
> 
> Thank you for your consideration of this matter.
> 
>    -Chas
> 
> --
> Charles Dawson
> Senior Engineering Manager
> NC-Verilog Team
> Cadence Design Systems, Inc.
> 270 Billerica Road
> Chelmsford, MA  01824
> (978) 262 - 6273
> chas@cadence.com
> 
> 
> --
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