[sv-bc] Mantis 1831: JEITA: 22.2.2.2 Module port headers clarification

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Tue Jun 12 2007 - 03:29:05 PDT
  

Hi,

We discussed this in the SV-BC meeting yesterday.

The issue description is,

In the JEITA review of the merged LRM, they found the following issue
with section 22.2.2.2:

"""It shall be illegal for a module declaration to mix the
port_reference port lists of non-
ANSI style module headers with the list_of_port_declarations ports lists
of ANSI style headers."" should be ""It shall be illegal for a module
declaration to mix the port_reference port lists of non-
ANSI style module headers with the list_of_port_declarations ports lists
of ANSI style headers in one module"" to explicitly show that the
mixture of non-ANSI and ANSI in one module is prohibited."

The text in question was added by Stu in Draft 3.

But the first paragraph of that same sub-clause, 22.2.2.2, says,

An alternate syntax that minimizes the duplication of data can be used
to specify the ports of a module. Each

module shall be declared either entirely with the list of ports syntax
as described in 22.2.2.1 or entirely using

the list_of_port_declarations as described in this subclause.

 

That seems to contain the same information as the paragraph in question,
which is new text. Therefore, I suggest simply deleting that new
paragraph ("It shall be illegal for ...").

As a side issue, for consistency with other places, as in Mantis 1597,
that first paragraph should be slightly reworded as,

An alternate syntax that minimizes the duplication of data can be used
to specify the ports of a module. Each

module shall be declared either entirely with the list_of_ports syntax
as described in 22.2.2.1 or entirely with

the list_of_port_declarations syntax as described in this subclause.

 

Shalom

Shalom Bresticker

Intel Jerusalem LAD DA

+972 2 589-6852

+972 54 721-1033 

 


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Received on Tue Jun 12 03:31:09 2007

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