Cliff's Votes - Yes to all except: 1064, 1400, 1641 This was a pretty hefty email vote, especially for DAC week when many of us were tied up from down to dusk most of the week. Regards - Cliff SVDB 965 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=965 SVDB 1004 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1004 SVDB 1064 ___Yes _X_No http://www.eda.org/svdb/bug_view_page.php?bug_id=1064 I have always understood that one could continue the text by ending with " followed by , and the next line starting with " I would like to hear everybody's opinion on this. SVDB 1101 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1101 SVDB 1111 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1111 Seems somewhat unnecessary but I can vote yes. SVDB 1143 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1143 SVDB 1257 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1257 Interesting bit of snooping on the part of Shalom! SVDB 1388 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1388 SVDB 1400 ___Yes _X_No http://www.eda.org/svdb/bug_view_page.php?bug_id=1400 I highly disagree. I believe a default mode should be specified and I now believe that default mode should be (a) not (b). If (b) is allowed to be the default, one can now turn on SystemVerilog compilation for an existing Verilog-2001 model and have it fail. If we claim to be backward compatible, this should not be the case. SVDB 1497 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1497 SVDB 1499 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1499 SVDB 1505 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1505 SVDB 1562 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1562 SVDB 1589 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1589 SVDB 1597 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1597 SVDB 1606 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1606 SVDB 1620 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1620 SVDB 1641 ___Yes _X_No http://www.eda.org/svdb/bug_view_page.php?bug_id=1641 Too complex for a simple email vote. This is not an errata, this is an enhancement. Should be discussed in committee. SVDB 1644 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1644 SVDB 1660 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1660 SVDB 1666 _X_Yes ___No Much nicer formatting, too! http://www.eda.org/svdb/bug_view_page.php?bug_id=1666 SVDB 1746 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1746 SVDB 1748 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1748 SVDB 1749 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1749 SVDB 1762 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1762 SVDB 1783 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1783 SVDB 1788 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1788 SVDB 1807 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1807 SVDB 1821 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1821 SVDB 1825 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1825 SVDB 1831 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1831 SVDB 1850 _X_Yes ___No http://www.eda.org/svdb/bug_view_page.php?bug_id=1850 ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification Training -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sun Jun 10 18:08:57 2007
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