[sv-bc] lrm references to verilog-xxxx, systemverilog-xxxx

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Fri Jun 01 2007 - 06:08:25 PDT
  

Hi,

In Draft 3, 1.1 says,

- SystemVerilog-2005 refers to IEEE Std 1800-2005 [B5]4 for the
SystemVerilog standard.

- SystemVerilog 3.1a refers to the Accellera SystemVerilog Language
Reference Manual, a pre-cursorto SystemVerilog-2005 [B1] .

- Verilog refers to IEEE Std 1364-2005 for the Verilog HDL.

- Verilog-2005 refers to IEEE Std 1364-2005 [B5] for the Verilog HDL.

- Verilog-2001 refers to IEEE Std 1364-2001 [B4] for the Verilog HDL.

- Verilog-1995 refers to IEEE Std 1364-1995 [B3] for the Verilog HDL.

 

SystemVerilog-2005, Verilog-2005, Verilog-2001, and Verilog-1995 are all
unofficial terms.

"SystemVerilog-2005" is used only here in the description of SV 3.1a.

"Verilog-1995" and "Verilog-2005" are used nowhere else.

"Verilog-2001" is used only in C.3.1, where it says, "Prior to the
acceptance of IEEE Std 1364-2001 (Verilog-2001)", and there it can be
deleted.

The reference to SystemVerilog-2005 here in the description of SV 3.1a
can simply be changed to IEEE Std 1800-2005.

I think all the references to these 4 terms should be deleted.

By the way, in

- SystemVerilog 3.1a refers to the Accellera SystemVerilog Language
Reference Manual, a pre-cursor to SystemVerilog-2005 [B1] .

the reference [Bn] is presumably supposed to refer to SV 3.1a, so it
should appear earlier, as follows:

-     SystemVerilog 3.1a refers to the Accellera SystemVerilog Language
Reference Manual [B1], a pre-cursor to IEEE Std 1800-2005.

 

 

That leaves us with 

Throughout this standard, the following terms apply:

- SystemVerilog refers to the unified Verilog base language (IEEE Std
1364) with the SystemVerilog extensions to Verilog. That is,
SystemVerilog is inclusive of both IEEE Std 1364-2005 Verilog and the
IEEE Std 1800-2005 extensions to Verilog.

- SystemVerilog 3.1a refers to the Accellera SystemVerilog Language
Reference Manual [B1], a pre-cursor to IEEE Std 1800-2005.

- Verilog refers to IEEE Std 1364-2005 for the Verilog HDL.

 

Another point is that Clause 2 (Normative References) includes
references to 1364-2001, 1364-2005, and 1800-2005.

Annex R (Bibliography), which is informative, includes references to all
these and also to 1364-1995. A reference should not appear in both.
Either the reference is normative or informative. I suggest to delete
all of these from Annex R, leaving SV 3.1a there, and move 1364-1995 to
Clause 2 with the rest.

Thanks,

Shalom

Shalom Bresticker

Intel Jerusalem LAD DA

+972 2 589-6852

+972 54 721-1033 

 


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Received on Fri Jun 1 22:29:17 2007

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