RE: [sv-bc] P1800/D3 : 9.2 Structured procedures

See also http://www.eda-stds.org/sv-ec/hm/4283.html .

-- Brad 

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Gran, Alex
Sent: Thursday, May 31, 2007 2:35 PM
To: stuart@sutherland-hdl.com
Cc: sv-bc@eda.org
Subject: [sv-bc] P1800/D3 : 9.2 Structured procedures

Sec 9.2
Minor typo, I think procedure should be singular not plural in this
sentence:
 
	The initial and always procedures are enabled at the beginning
of a simulation. The initial
	procedure shall execute only once, and its activity shall cease
when the statement has finished. In 
	contrast, an always **procedures** shall execute repeatedly ,
and its activity shall cease only when
	the simulation is terminated.

 

Sec 9.2.3
All occurrences of the phrase "final block" were changed to "final
procedure" with the exception of the last 2 paragraphs of 9.2.3

Was this intentional or an oversight?

	SystemVerilog **final blocks** execute in an arbitrary but
deterministic sequential order. This is possible
	because **final blocks** are limited to the legal set of
statements allowed for functions.
	NOTE-SystemVerilog does not specify the ordering in which
**final blocks** are executed, but implementations should
	define rules that preserve the ordering between runs. This helps
keep the output log file stable because **final 	blocks** are
mainly used for displaying statistics.


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