[sv-bc] overloading an assignment operator

Hi,

 

I have a question regarding assignment operator and its overloading. In
Verilog and System Verilog LRM, I did not find "=" operator in the list
of binary operator. In C and C++, this is given. Can anyone please point
me any LRM verse which says that assignment is a binary operator? By
nature, it obviously looks as binary operator.

 

Now when we overload an operator, the SV LRM does not pose any
restriction on the no of arguments of the bounded function. For example,
in C++ if we overload a binary operator through a non-static member
function of a class then the operator argument should be one in number
but if it is static member function of the class then the function
should have two arguments (for two operands).

 

Since SV don't have any such restriction, is the following SV Testcase
valid?

===========

typedef struct {

    bit[1:0] Real;

    bit[1:0] imaginary;

} complex; 

 

function complex assgn(complex c, int i);

    c.Real = i;

    assgn.Real = c.Real;

    assgn.imaginary = c.imaginary;

endfunction

 

module op_overload1( 

                               input  int            in, 

                               input  bit            clk, 

                               output complex        out1); 

 

            bind = function complex assgn(complex, int);

            complex temp;

 

            always@(clk)

            begin;

                        

                        out1  = (temp = in);

            end

endmodule

 

 

Thanks,

Subhamoy


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