Re: [sv-bc] part selects on arbitrary expressions

>> reg signed [31:0] r,s;

>This view is also inconsistent with the treatment of  assign y = x +
s[63:0];
>Unless I am horribly mistaken, s is not first extended to 128 bits and
then truncated.

The MSB of that part-select is clearly out-of-range.  For example, the
following test case should display x's, not 0's.

module test;
reg [31:0] lhs;
reg [15:0] rhs;
initial begin
  rhs = 16'h0000;
  lhs = rhs[31:0];
  $displayb(lhs[31:16]);
end
endmodule 

-- Brad


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