RE: [sv-bc] part selects on arbitrary expressions

Ah, yes, thanks for reminding us of that nice fix.  Verilog-XL used to
allow such things to support schematic capture software that was [0]
happy; so it used to have to be OK to put (and simulators had to accept)
[0] on every scalar.  With 2005 we ceremoniously buried the last SCALD
station, and this syntax. 

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brad
Pierce
Sent: Wednesday, March 07, 2007 11:23 AM
To: sv-bc@eda-stds.org
Subject: RE: [sv-bc] part selects on arbitrary expressions

>I submit that the disturbing thing here is the silent treatment of a
scalar
>as a one element vector.

According to IEEE Std 1364-2005:5.2.1, 

   "A bit-select or part-select of a scalar [...] shall be illegal."

See

   http://www.boyd.com/1364_btf/report/full_pr/261.html

-- Brad


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