RE: [sv-bc] part selects on arbitrary expressions

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Tue Mar 06 2007 - 09:03:53 PST
Hi, Adam.

 

I think that would not solve Yulik's case where the expression is not a
simple packed array, as the brackets make it into a concatenation and
then only what is legal into a concatenation would be legal here. 

 

Shalom

 

________________________________

From: Adam Krolnik [mailto:adam.krolnik@verisilicon.com] 
Sent: Tuesday, March 06, 2007 6:48 PM
To: Bresticker, Shalom
Cc: Feldman, Yulik; sv-bc@eda.org
Subject: Re: [sv-bc] part selects on arbitrary expressions

 



Hello Shalom;



>For example, "$select(a+b,3,3)" makes it clear that a+b is a
self-determined expression,



In verilog, use of braces {} provide a context for self determination of
expressions.

Thus I would recommend that instead of (a+b)[3] or $select(a+b, 3,3)
you consider



    {a + b}[3]





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