Jonathan Bromley wrote: > Françoise, > [...] > interface I; > logic L; > modport MP(output L); > endinterface : I > [...] > Suppose, then, that we accept this and so we are > permitted only one instance of M: > > module Top2; > I inst_I(); > M inst_M(inst_I.MP); > endmodule : Top2 > > What happens if I now force Top2.inst_I.L? Is that > force reflected in the value of mp.L as seen inside > Top2.inst_M ? No, it wouldn't be due to the continuous assign semantics. There are no concept of variable port collapsing in the LRM. I think that the answer is different if "L" was a net since there should only be one simulated net in the design and the force acts on the *net* so its effect is visible even on the output port. I have, for a long time, thought that 1364 is pretty weak in terms of the dealing with the interactions between force and net collapsing. 1364 says that collapsing is "permissible" but the behavior of force across ports is not the same if one doesn't collapse (although one could likely approximate the effects with enough work). Gord. -- -------------------------------------------------------------------- Gordon Vreugdenhil 503-685-0808 Model Technology (Mentor Graphics) gordonv@model.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Mar 2 06:58:44 2007
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