RE: [sv-bc] part selects on arbitrary expressions

BTF 474 (Mantis 1197)

> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Maidment, Matthew R
> Sent: Tuesday, February 20, 2007 10:56 PM
> To: sv-bc@server.eda.org
> Cc: Adam Krolnik
> Subject: Re: [sv-bc] part selects on arbitrary expressions
> 
> From Adam Krolnik:
> 
> 
> >[Adam Krolnik <adam.krolnik@verisilicon.com>]
> >
> >
> >
> >I believe that 'anonymous part selects' was proposed as part of
1364...
> >
> >out = {a & b ? a+b : c+d}[3:0];
> >
> >
> >--
> >    Soli Deo Gloria
> >    Adam Krolnik
> >    Director of Design Verification
> >    VeriSilicon Inc.
> >    Plano TX. 75074
> >    Co-author "Assertion-Based Design"
> >
> >
> >--
> >This message has been scanned for viruses and
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> >
> >
> 
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