Hi,
Recently I have come across some designs where some invalid
semantically wrong verilog code is written in dead/unreachable portion
of generate region. LRM is not clear enough which semantic check should
be done at elaboration time and which in parsing time. And also
different tools are behaving differently in different scenario. I think
there should be clear guideline in the LRM to eliminate the whole
confusion.
Case 1:
module top;
integer x;
generate if (0) begin:b
if (x) begin:c
end
end
endgenerate
endmodule
Here 'x' has to be constant expression but placed in unreachable
portion of generate. Synopsys VCS is passing it, but MTI-Vlog is
failing.
Consider another similar case:
module top;
integer x;
generate if (0) begin:b
if (x) begin:c
reg[x:0] r;
end
end
endgenerate
endmodule
For the reg declaration, the 'x' has to be again constant but placed in
unreachable portion of generate. But here VCS and Vlog both are failing
here. So VCS is not consistent enough to skip all types of semantic
checks in generate region. That makes a lot of confusion in parser
writing as well as design writing. LRM has to have some words for that.
Regards
Surya.
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Received on Wed Feb 21 20:44:55 2007