[sv-bc] Behaviour of ref port

Hi,

In the Std 1800-2005 LRM section 19, ref has been used in context with 
variables. But according to BNF:

ansi_port_declaration ::= [ net_port_header | interface_port_header ] 
port_identifier { unpacked_dimension }
net_port_header ::= [ port_direction ] net_port_type
port_direction ::= input | output | inout | ref

So we can have a declaration like :

module top(ref wire a);
endmodule

Some tools are failing giving error like : "ref port cannot be of net type"
Some tools are passing.

What is the correct behaviour for ref ?

Thanks,
Sarani



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