>From: Kevin Cameron <dkc@grfx.com> > >Verilog-AMS isn't supposed to be an "external" HDL, it is supposed to be >getting integrated into SystemVerilog at some point. > >Or is there no intention to integrate it? I would not expect it to be integrated any time soon. However, it is still a good idea to try to bring the languages into closer alignment. Consistency will help users who are using both languages, as well as making any eventual integration easier. Some tiny steps were made in 1364-2005 with this in mind. Steven Sharp sharp@cadence.comReceived on Tue Dec 5 14:30:38 2006
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