RE: [sv-bc] Re: [sv-ec] List of port expressions

I'm confused.

I think Daniel's example is in principle legal, except that it needs to
appear like this:

module m ( .a(sig[0] ) ;

input [1:0] sig ;

endmodule

The key is that the name being declared as input is not the
port_identifier a, but rather the identifier sig in port_reference
sig[0].

In 1364-2005, 12.3.3 shows examples of this syntax, but the examples are
not very clear.

An example from there is:

module mixed_direction (.p({a, e}));
input a; // p contains both input and output directions.
output e;



> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Brad Pierce
> Sent: Sunday, November 12, 2006 10:12 AM
> To: sv-bc@server.eda.org
> Cc: Neil.Korpusik@sun.com; danielm@aldec.com.pl
> Subject: [sv-bc] Re: [sv-ec] List of port expressions
> 
> Daniel,
> 
> Following up on
> 
>     http://www.eda-stds.org/sv-ec/hm/3792.html
> 
> the intent of the SV-BC on Sept. 29, 2003 was to enhance only the
> 2001-style port declarations, not the 1995-style port declarations.
So
> the following was intentionally forbidden.
> 
>     module(.a(sig[0])); /*
>       input a;
>       wire [1:0] sig;
>     endmodule
> 
> The proposal was made by Dave Rich in
> 
>
http://www.eda-stds.org/sv-bc/hm/att-1065/02-modport_expressions.pdf
> 
> -- Brad
> 
> -----Original Message-----
> From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Neil
> Korpusik
> Sent: Friday, November 10, 2006 11:19 AM
> To: SV_EC List
> Cc: danielm@aldec.com.pl
> Subject: [sv-ec] List of port expressions
> 
> <forwarding email from Daniel M.>
> 
> 
> -------- Original Message --------
> Subject: List of port expressions
> Date: Thu, 09 Nov 2006 10:56:21 +0100
> From: danielm <danielm@aldec.com.pl>
> To: owner-sv-ec@eda.org
> 
> SV defines list of port expressions (19.9). This is defined only for
> ANSI style headers. This is mistake in syntax production?
> 
> port ::=
> [ port expression ]
> | . port identifier ( [ port_expression ] )
> 
> ansi_port_declaration ::=
> [ net_port_header | interface_port_header ] port_identifier {
> unpacked_dimension }
> | [ variable_port_header ] port_identifier { variable_dimension } [ =
> constant_expression ]
> | [ net_port_header | variable_port_header ] . port_identifier ( [
> expression ] )
> 
> 
> Diference in ANSI_port and port definition which I dont understand is:
> -for ANSI: port_identifier ( [ expression ]
> - for nonANSI :. port_identifier ( [ port_expression ] )
> 
> Port expression is limited only to port reference.
> So according to LRM I cannot have in non ANSI style:
> module(.a(sig[0])); /*
>   input a;
>   wire [1:0] sig;
> endmodule
> 
> But in ANSI style i can have:
> module(input .a(sig[0]));/**
>   wire [1:0] sig;
> endmodule
> 
> Question is : is really (*) forbidden?
> 
> DANiel
> 
>