Re: [sv-bc] Mantis 1571: Add default values for macro arguments

Intel made at least three reasonable, still unresolved, SV-BC
enhancement requests during the P1800 balloting

   http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0000696
   http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0000693
   http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0000694

And, as described in http://www.eda-stds.org/sv-ac/hm/2508.html , there
are now many additional, reasonable ideas for enhancing the language
from Intel in the Attached File of

   http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001530

-- Brad

-----Original Message-----
From: Steven Sharp [mailto:sharp@cadence.com] 
Sent: Thursday, October 19, 2006 1:28 PM
To: sv-bc@eda.org; Brad.Pierce@synopsys.COM
Subject: Re: [sv-bc] Mantis 1571: Add default values for macro arguments


>From: "Brad Pierce" <Brad.Pierce@synopsys.com>

>Maybe weaknesses of the core SV language are abusing the users, so they

>are attempting to work around those weaknesses with macros.  If so, 
>then we should strengthen the core SV language, not the macro language.

Which was Dave's point.

There are other possibilities.  They may be working around limitations
of a particular partial implementation of SV.

So the question for Shalom is, what are these complex macro mechanisms
being used for?

Steven Sharp
sharp@cadence.com