[sv-bc] Re: [sv-ec] Pattern matching in if statements

 

-----Non-member Submission-----
On Behalf Of Moumita Das
Sent: Monday, October 16, 2006 2:01 AM

Hello,

LRM -IEEE Std 1800-2005 IEEE Standard System Verilog sec 10.4  describes
the rules for conditional_statement which is-

conditional_statement ::=
           if ( cond_predicate ) statement_or_null [ else
statement_or_null ]
           | unique_priority_if_statement

unique_priority_if_statement ::=
           [ unique_priority ] if ( cond_predicate ) statement_or_null
          { else if ( cond_predicate ) statement_or_null }
           [ else statement_or_null ]

cond_predicate ::=
           expression_or_cond_pattern { &&& expression_or_cond_pattern }
expression_or_cond_pattern ::=
           expression | cond_pattern
cond_pattern ::= expression matches pattern

But in  Sec -10.4.1.2  of same LRM I have found an example -
if     ( e matches (tagged Jmp .j)* ,*   j matches (tagged JmpC 
'{cc:.c,addr:.a}) )
...
else

Which does not correspond to the above BNF .

Anyone please  tell me whether this example is valid one  or not?
And if it is valid then from which rule it is derived and how?

Thanks .
Moumita