[sv-bc] RE: [sv-ac] expect statement inside function

Even without the footnote, the rules of 1364-2005 10.4.4 a) apply. Only
the rules of 10.4.4 c) and d) have been removed by 1800-2005.

Dave


> -----Original Message-----
> From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org]
On
> Behalf Of Bresticker, Shalom
> Sent: Monday, October 16, 2006 4:38 AM
> To: Soumya Jyoti Wadader; sv-ac@server.eda.org
> Cc: sv-bc@server.eda.org
> Subject: RE: [sv-ac] expect statement inside function
> 
> Yes, "function_statement ::= statement", but in the 1364-2005 BNF,
that
> has a footnote:
> 
> "1) Function statements are limited by the rules of 10.4.4."
> 
> That footnote is missing from the 1800 BNF, probably because section
> 10.4.4 of 1364-2005 was not copied into 1800.
> 
> Shalom
> 
> 
> > -----Original Message-----
> > From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org]
> On
> > Behalf Of Soumya Jyoti Wadader
> > Sent: Monday, October 16, 2006 1:25 PM
> > To: sv-ac@server.eda.org
> > Subject: [sv-ac] expect statement inside function
> >
> > I have a quary regarding an 'expect' statement  inside function.
> > According to v2k LRM 1364_2001  LRM section:
> >                                                   10.3.4 Function
> rules
> >                                                           a) A
> function
> > definition shall not contain any time-controlled statements that
> is,any
> > statements introduced with #,@,or wait .
> >
> > But IEEE SV LRM says that:
> >             A.2.6 (BNF)
> >                    A.2.6 Function declarations
> >                                function_body_declaration ::=
> >                                                            {
> > function_statement_or_null }
> >                                function_statement_or_null ::=
> >
> > function_statement
> >                                   function_statement ::= statement
> >                                statement ::= [ block_identifier : ]
{
> > attribute_instance } statement_item
> >                                   statement_item ::= |
> > expect_property_statement
> >                       A.2.10    expect_property_statement ::=
> >                                                        expect (
> > property_spec ) action_block
> >
> > So, from SV LRM it is clear that we can use 'expect' inside
function,
> In
> > IEEE SV LRM section: 17.16, says that "The expect statement can be
> > incorporated in any procedural code, including tasks or class
> methods."
> > I have an example where I use 'expect' statement as :
> >
> > module expect9 ( clk,  reset,  out );
> >     input clk;
> >     input reset;
> >     output[7:0] out;
> >     wire clk;
> >     wire reset;
> >     reg[7:0] out;
> >     always @( posedge clk or posedge reset )
> >       begin
> >            if( reset == 1'b1 )
> >            out <= 0;
> >            else
> >                out <= out + 1;
> >       end
> >
> > sequence seq;
> > @(posedge clk) out[0] ##1 !out[0] ##2 (out[2])[*4];
> >  endsequence
> >
> >  property p1;
> > @(posedge clk)
> > reset ##1 !reset |=> seq ##1 (!out[6])[*2] ;
> >  endproperty
> >
> > function reg assert_func (input bit clk);
> > expect (p1)
> >    begin
> >      $display(" EXPECT STATMENT HOLDs INSIDE THE FUNCTION");
> >      return 0;
> >    end
> >  else
> >    begin
> >     $display(" EXPECT STATMENT DOES'NT HOLDs");
> >     return 1;
> >    end
> > endfunction
> >
> >  always@(posedge clk)
> >   begin
> >    reg r;
> >    r = assert_func(clk);
> >     end
> > endmodule
> >
> >  function does not allow any time control expression, so how can I
use
> > 'expect' statement inside function?
> >
> >