RE: [sv-bc] Re: [sv-ec] timeunit Declaration Verbosity

From: Bresticker, Shalom <shalom.bresticker_at_.....>
Date: Sun Oct 15 2006 - 07:11:58 PDT
I personally go the other way and tell people not to use timescales at
all. My experience is that the more modules which have timescales, the
more troubles you have.

Shalom

> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Clifford E. Cummings
> Sent: Tuesday, October 10, 2006 9:13 PM
> To: sv-ec@server.eda.org; sv-bc@server.eda.org
> Subject: [sv-bc] Re: [sv-ec] timeunit Declaration Verbosity
> 
> Hi, All -
> 
> Heath first sent this to the EC but perhaps it would better reside in
> the BC(?)
> 
> Heath brings up what is also my primary objection to the new timeunit
> / timeprecision pair of keywords.
> 
> Due to its convenience, I prefer and I recommend to students that the
> add a `timescale in front of every module that contains time delays
> (due to compile-order issues). The one nice feature for the new
> timeunit-timeprecision keywords is that when placed in a module, they
> are local to the module and turn off at the end of the module,
> allowing simulations to return to their regularly scheduled
> `timescale. For that reason, I recommend the new more verbose
> constructs to IP providers, so that their code will not change any
> other active `timescale in the user's design.
> 
> If I could combine the timeunit 1ns / 1ns; as Heath has recommended,
> then I would switch my allegiance and favor this new construct. I
> prefer the "/" separator just because it is like the `timescale
> separator but I could go with either option described by Heath.
> 
> Thoughts?
> 
> Regards - Cliff
> 
> At 04:20 PM 9/25/2006, Heath Chambers wrote:
> 
> >Was the verbosity of the new timeunit and timeprecision
> >declarations brought up when they were first introduced?
> >
> >I'm used to putting `timescale in front of every module
> >that I have that has a time delay inside; but if I want
> >to follow that same convention using the new declarations,
> >a significant amount of extra typing is required.
> >
> >How difficult would it be (from a vendor perspective and
> >from a committee perspective) to allow something like
> >the following one line shortcut:
> >   timeunit time_literal [ / time_literal];
> >   OR
> >   timeunit time_literal [ , time_literal];
> >
> >The first time_literal would be the time unit and the
> >optional second time_literal would be the time precision.
> >The separator could either be the / like the `timescale
> >directive or a comma, which ever the committee decided
> >would be best.
> >
> >Example:
> >   timeunit 1ns/10ps;
> >   ==
> >   timeunit 1ns;
> >   timeprecision 10ps;
> >
> >Thanks,
> >-- Heath
> >
> >####################################
> >|                                  |
> >| HMC Design Verification, Inc.    |
> >|                                  |
> >| Heath Chambers                   |
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> >####################################
> 
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, SystemVerilog, Synthesis and Verification Training
Received on Sun Oct 15 07:12:40 2006

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