Re: [sv-bc] Email Ballot Due Sep 28

Cliff's Votes:

Yes to all but the last proposal. Modification proposed.

At 11:39 PM 9/21/2006, you wrote:

>-You have 1 week to respond (Midnight PDT September 28)
>-An issue passes if there are zero NO votes and half of the eligible
>  voters respond with a YES vote.
>-If you vote NO on any issue, your vote must be accompanied by a reason.
>  The issue will then be up for discussion during a future conference
>call.
>
>As of the September 11th meeting, the eligible voters are:
>
>Brad Pierce
>Shalom Bresticker
>Cliff Cummings
>Surrendra Dudani
>Mark Hartoog
>Francoise Martinolle
>Karen Pieper
>Dave Rich
>Steven Sharp
>Gordon Vreugdenhil
>Doug Warmke
>Stu Sutherland
>Logie Ramachandran
>Don Mills
>Rishiyur Nikhil
>Heath Chambers
>
>0967, 0982, 1119, 1209, 1337, 1341, 1493,
>1496, 1529, 1534, 1538, 1539, 1540, 1554
>
>SVDB 0967 _X__Yes   ___No
>http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0000967
>
>SVDB 0982 _X__Yes   ___No
>http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0000982
>
>SVDB 1119 _X__Yes   ___No
>http://www.verilog.org/svdb/bug_view_page.php?bug_id=00001119
>
>SVDB 1209 _X__Yes   ___No
>http://www.verilog.org/svdb/bug_view_page.php?bug_id=00001209
>
>SVDB 1337 _X__Yes   ___No (Close as duplicate of 1334)
>http://www.verilog.org/svdb/bug_view_page.php?bug_id=00001337
>
>SVDB 1341 _X__Yes   ___No
>http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001341
>
>SVDB 1493 _X__Yes   ___No
>http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001493
>
>SVDB 1496 _X__Yes   ___No
>http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001496
>
>SVDB 1529 _X__Yes   ___No
>http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001529
>
>SVDB 1534 _X__Yes   ___No
>http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001534
>
>SVDB 1538 _X__Yes   ___No
>http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001538
>
>SVDB 1539 _X__Yes   ___No
>http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001539
>
>SVDB 1540 _X__Yes   ___No
>http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001540
>
>SVDB 1554 ___Yes   _X__No
>http://www.eda-stds.org/svdb/bug_view_page.php?bug_id=0001554

I would like the wording clarified a little more. I believe the 
intent is to propose:

PROPOSED:
It shall be legal to call any of these query functions within a 
constant expression if the call would be legal in an expression, the 
first argument is a fixed-size type or is an expression of some 
fixed-size type, and the optional dimension expression, if there is 
one, is a constant expression.

AMENDED PROPOSAL:
It shall be legal to call any of these query functions within a 
constant expression if all three of the following conditions are 
true: (1) the call would be legal in an expression, (2) the first 
argument is a fixed-size type or is an expression of some fixed-size 
type, and (3) the optional dimension expression, if there is one, is 
a constant expression.

If the amended wording is wrong, then I clearly did not understand 
the proposed wording and it needs to be updated. The Sentence is 
complex enough to justify the 1-3 listing with clarification.

Regards - Cliff

>--
>Matt Maidment
>mmaidmen@ichips.intel.com
>

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training