RE: [sv-bc] assignment to input

Shalom,

 

I said in a later post that that it cannot default to a wire kind as the
sentence you refer to demands.

 

We would have to either:

1.	define all data types as valid for wire kinds
2.	change the default not to be a wire kind for those types not
supported for wire kinds
3.	make it an error (not backwards compatible with all three
previous Accellera standards)
4.	Remove the special default kind for input and inout ports and
have them match the default kinds everywhere else.

 

Dave

 

 

________________________________

From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Bresticker, Shalom
Sent: Thursday, September 21, 2006 5:58 AM
To: Rich, Dave; sv-bc@server.eda-stds.org
Subject: RE: [sv-bc] assignment to input

 

Dave,

 

Where do you see that 'input bit a' or 'input real a' defaults to
variable?

 

The only sentence I see says that, "For input and inout ports, if the
port kind is omitted, then the port shall default to a net of net type
wire."

 

Thanks,

Shalom

 

________________________________

From: Rich, Dave [mailto:Dave_Rich@mentor.com] 
Sent: Monday, September 04, 2006 9:07 PM
To: Bresticker, Shalom; sv-bc@server.eda-stds.org
Subject: RE: [sv-bc] assignment to input

 

Prior to IEEE 1800-2005, input logic a, defaulted to a variable, which
meant it could not be coerced to an inout. Now it defaults to a wire of
type logic. 

 

However, input bit a, or input real a still does default to a variable
since we do not allow these types on wires.

 

As I said earlier, I don't like this new default.

 

input a has always defaulted to a wire. Now it defaults to a wire of
type logic.

 

Dave