> I think the phrase could be made more successful if it were phrased in > terms of bit significance, starting from LSB to MSB (indirectly > referring to the vector equivalent Steven mentioned) Would it not be better still if we had an explicit notion of the "equivalent vector" of any packed object? I suspect that would be useful in other situations too. By defining the equivalent vector to have a normalized subscript range [N-1:0] you could make it rather easy to rewrite 19.12.5. I'm not suggesting that "equivalent vector" be defined in 19.12.5, but rather that it be a definition quite early in the LRM that can be used in discussion of *any* packed object. Nor am I suggesting that the equivalent vector be required to exist as a real physical object. It would be only a convenient (and well-defined) fiction in the LRM. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. reserves all rights of privilege in respect thereof. It is intended for the use of the addressee only. If you are not the intended recipient please delete it from your system, any use, disclosure, or copying of this document is unauthorised. The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Received on Wed Sep 20 03:05:41 2006
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