RE: [sv-bc] Is "var" required for real ports?

As I mentioned in http://www.eda-stds.org/sv-bc/hm/5044.html, 

module m(input real r);

now defaults a wire of type real. Since we do not allow real wires, you
would either have to add the var keyword, or change the data type to one
that is legal for reals.

This is backward incompatible with 3.1a

Dave


> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Stuart Sutherland
> Sent: Friday, September 15, 2006 9:39 AM
> To: sv-bc@server.eda.org
> Subject: [sv-bc] Is "var" required for real ports?
> 
> 
> 
> I has been brought to my attention that one SV simulator requires a
"real"
> module port to be declared as "var real", and other simulator as just
> "real".  I cannot find any justification in the LRM for "var" being
> required
> to declare a real port.  This difference in simulators is
third-hand...I
> don't have the product licenses to test the claim.
> 
> If "var" is required, can anyone point me to exactly where that is
> specified
> in the LRM?
> 
> Stu
> ~~~~~~~~~~~~~~~~~~~~~~~~~
> Stuart Sutherland
> stuart@sutherland-hdl.com
> +1-503-692-0898
>