[sv-bc] Does named modport port represent any data type?

From: Surya Pratik Saha <spsaha_at_.....>
Date: Fri Sep 15 2006 - 00:26:25 PDT

Hi,
In SV 1800 LRM, following e.g. is given (section no. 20.4.4 Modport expressions, page no. 359):
interface I;
logic [7:0] r;
const int x=1;
bit R;
modport A (output .P(r[3:0]), input .Q(x), R);
modport B (output .P(r[7:4]), input .Q(2), R);
endinterface
module M ( interface i);,
initial i.P = i.Q;
endmodule
module top;
I i1;
M u1 (i1.A);
M u2 (i1.B);
initial #1 $display("%b", i1.r); // displays 00010010
endmodule

Here hierarchical reference is applied on named modport port 'P' and 'Q'. But do they represent any data type?

LRM is not clear on that. If we consider equivalent e.g. with named port in module port declaration corresponding to Verilog 2005 LRM:
module top (.A(x), .B(y));
        input x,y;
endmodule

module test;
        assign top.A = 1;
endmodule

This is invalid case. As  'A' does not represent any data type. So I think the e.g. provided in SV LRM is wrong.

-- 
Regards
Surya.

  Received on Fri Sep 15 00:27:24 2006