[sv-bc] Proposal for Mantis 1119: 19.3: Preprocessor macros within strings

Here is a proposal for Mantis 1119:
 
In 1364-2005, add at the end of 19.3.1:
 
However, macro substitution and argument substiution shall not occur
within strings. For example,
module main; 
`define HI Hello 
`define LO "`HI, world" 
`define H(x) "Hello, x" 
initial begin
  $display("`HI, world"); 
  $display(`LO); 
  $display(`H(world)); 
endmodule 

will print: 

`HI, world

`HI, world 
Hello, x
Shalom 
 
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Mantis - SystemVerilog Errata
Viewing Bug Advanced Details 	
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ID: 	Category: 	Severity: 	Reproducibility: 	Date
Submitted: 	Last Update: 	
1119 	V-1364 	major 	always 	12-04-05 09:51 	08-14-06 07:18 	
________________________________

Reporter: 	pieper 	Platform: 		 	
Assigned To: 	shalom 	OS: 		 	
Priority: 	normal 	OS Version: 		 	
Status: 	assigned 	Product Version: 		 	
Product Build: 		Resolution: 	open 	 	
Projection: 	none 	Duplicate ID: 		 	
ETA: 	none 	 	
Type: 	Errata 	
________________________________

Summary: 	19.3: Preprocessor macros within strings 	
Description: 	Was:
http://www.boyd.com/1364_btf/report/full_pr/364.html

I'm searching in the IEEE1364-2001 for the statement or string of
statements that says that preprocessor macros cannot appear in strings.
I'm not finding such a thing. Here's an example: 

module main; 
`define HI Hello 
initial $display("`HI, world."); 
endmodule 

Should I expect to print: 

`HI, world 

Or should substitution be done, to get: 

Hello, world. 

The standard says "The text specified for macro text shall not be 
split across the following lexical tokens: ..." and includes strings. 
But macro text can clearly be a complete string, number, whatever. 

I believe the intent is that macro substitution *not* happen within 
lexical strings. Otherwise, absurdities can occur. This should be 
said explicitly. Perhaps this note can be added: 

NOTE: Strings are lexical units, so macros are not expanded or 
recognized within quoted strings. For example, "`HI, world" is 
not scanned for directives or macros. 
-- 
Steve Williams
steve at icarus.com
	
Steps To Reproduce: 		
Additional Information: 	From: Stephen Williams
<steve@icarus.com> 
Date: Sun, 15 Jun 2003 17:30:42 -0700 

module main; 
`define HI Hello 
initial $display("`HI, world."); 
endmodule 

Actually, here I am following up to my own errata report. It appears 
that at least one compiler in the wild (besides Icarus Verilog) does 
indeed do macro substitution within strings. 

<http://www.icarus.com/cgi-bin/ivl-bugs?findid=622> 

This suggests that I'm not losing it completely, and perhaps macro 
substitution within strings is legal. That's tricky business. To wit: 

`define foo "Hello" 
initial $display("`foo makes a mess"); 

One might simply call this a You-get-what-you-deserve type of coding 
error, given my original observation that it is not explicitly 
prohibited, and in this case macro expansion within strings should 
be explicitly allowed within strings. 

NOTE: Macros are substituted within lexical strings. A macro 
value that contains double-quote characters may therefore cause 
an error if it is itself (or if it contains) a quoted string, 
as the double-quotes within the macro would interfere with the 
lexical string itself. 

Personally, I prefer not allowing macro substitution within strings. 


From: Michael McNamara <mac@verisity.com> 
Date: Mon, 16 Jun 2003 16:37:29 -0700 

Macros have always been substituted in strings in Verilog, since time 
began (I'm looking at a Verilog-XL 1.1a manual (March 1987), where 
this is documented on page 2-6). 


From: Stephen Williams <steve@icarus.com> 
Date: Mon, 16 Jun 2003 09:35:02 -0700 

mac@verisity.com said: 
> Macros have always been substituted in strings in Verilog, since time 
> began (I'm looking at a Verilog-XL 1.1a manual (March 1987), where 
> this is documented on page 2-6). 

That may be so, but I'm going by the written standard which is 
slightly vague on this matter. I don't have access to the expensive 
tools for comparison purposes, nor should the standard be left to 
lore, word-of-mouth and bug-compatibility. 

Anyhow, I'm just trying to make it language-lawyer clear. The current 
wording managed to confuse this C programmer twice. 


From: Shalom Bresticker <Shalom.Bresticker@motorola.com> 
Date: Mon, 16 Jun 2003 19:38:26 +0300 

Michael McNamara wrote: 

> Macros have always been substituted in strings in Verilog, since time 
> began (I'm looking at a Verilog-XL 1.1a manual (March 1987), where 
> this is documented on page 2-6). 

Such a statement does not appear in the Verilog-XL 5.0 manual, 
nor does it simulate that way in VXL 4.0: 

`define QQ aaaa 
module qq; 
initial 
$display(" `QQ "); 
endmodule 

The result is: 
`QQ 


From: Shalom Bresticker <Shalom.Bresticker@motorola.com> 
Date: Mon, 16 Jun 2003 19:48:57 +0300 

> The standard says "The text specified for macro text shall not be 
> split across the following lexical tokens: ..." and includes strings. 
> But macro text can clearly be a complete string, number, whatever. 

So I have interpreted that statement to mean that just as you can not
write an 
identifier name as: 

aa`BBBcc (although we would like to be able to do so) 

then you can also not write 

"aa `BBB cc" 


From: Steven Sharp <sharp@cadence.com> 
Date: Mon, 16 Jun 2003 18:40:13 -0400 (EDT) 

> Macros have always been substituted in strings in Verilog, since time 
> began (I'm looking at a Verilog-XL 1.1a manual (March 1987), where 
> this is documented on page 2-6). 

Mac, can you quote the text you are referring to from the 1.1a manual? 
The earliest I have is a 1.6c manual from June 1993, which doesn't say 
anything about it. The OVI 2.0 LRM from March 1993 also doesn't say 
anything about it. 

At any rate, a current version of Verilog-XL does not substitute macros
in strings. This might be a situation where Verilog has evolved since
time began. 	
Attached Files: 		

Bug Notes 	
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shalom    	
08-13-06 05:34    	
See 1338.