>From: "Brad Pierce" <Brad.Pierce@synopsys.com> >On the contrary, users deserve to get what they've always got. Legacy >code is indeed a legacy, and we can't afford to squander it. I agree that this is important. Let's look at the legacy situation. The vast majority of Verilog code does not depend on whether short- circuit execution is done. Any code that does is either relying on short-circuiting being done, or on it not being done. There is no way code can rely on it being undefined. There may be coders who accounted for it being undefined, but that just means that they wrote code that did not depend on whether it was done or not. So which behavior is this small amount of questionable legacy code relying on? Verilog-XL appears to do short-circuit evaluation of && and || operators, at least when there are function calls with side-effects involved so that it can be tested. That accounts for all the oldest legacy code. The other Verilog simulator I have access to does it also. There are others that I don't have access to, but I would not be surprised if almost all of them do it too. Perhaps others can comment on that. If my suspicions are correct, then all the legacy code for which this matters is dependent on short-circuiting. There is also another semi-legacy situation. There is legacy code out there in languages other than Verilog, which users may want to port to Verilog or SystemVerilog. Examples include C and Vera code. That job is simplified when the syntax is similar, as with conditions including && and ||, but only if the semantics are the same. >To me, it would make more sense to say that a side-effecting >expression shall not be the operand of an && or ||. If there is any legacy code out there relying on doing this, then such a rule would make this code illegal. That would be squandering that legacy code, to use your phrase. Steven Sharp sharp@cadence.comReceived on Sat Aug 12 15:47:55 2006
This archive was generated by hypermail 2.1.8 : Sat Aug 12 2006 - 15:48:04 PDT