Re: [sv-bc] [Fwd: Issues with IEEE 1364-2005]

A more natural syntax for linearized short-circuiting would be to add
defaults to the existing ?: syntax.

If it were legal to omit the then-leg or else-leg of an ?:

    A ? B   -->   A ? (|B) : 1'b0

    A ?: B  -->   A ? 1'b1 : (|B)

then, where the C language requires

    if (A && B && C) 

in Verilog one could write 

    if (A ? B ? C)

and where the C langauge requires

    if (A || B || C)

in Verilog one could write

    if (A ?: B ?: C)

because

  if (A ? B ? C)   --> if (A ? |(B ? (|C) : 1'b0) : 1'b0)

  if (A ?: B ?: C) --> if (A ? 1'b1 : |(B ? 1'b1 : (|C)))
 
-- Brad