Re: [sv-bc] [Fwd: Issues with IEEE 1364-2005]

I have to agree with Will.  I'm using Verilog-AMS as a replacement
for C for describing transistor models.  I'm not thinking of the
operands as hardware (logic gates) that evaluates expressions
independently.  I might, however, have expressions like
  if (rs != 0 && 1/rs < 1e20) begin
    // do something
  end
where "rs" is a real variable and 1/0 causes a math error in the
analog solver.  It's a real pain to have to re-write that as
  if (rs != 0) begin
    if (1/rs < 1e20) begin
      // do something
    end
  end

-Geoffrey


Brad Pierce wrote:
> 
> I don't see the "ambiguity".  Verilog is not C.  For example, the
> context-sensitive arithmetic of Verilog is completely different than in
> other programming languages.  Nowhere in the LRM is there even a hint
> that && and || behave as they do in C.  In Verilog, as in hardware,
> there is no specified evaluation order for operands.
> 
> -- Brad
> 
> -----Non-member submission-----
> From: Will Adams [mailto:wadams@freescale.com]
> Sent: Thursday, August 10, 2006 10:20 AM
> To: Steven Sharp
> Cc: sv-bc@eda.org; Brad.Pierce@synopsys.COM; michael.burns@freescale.com
> Subject: Re: [sv-bc] [Fwd: Issues with IEEE 1364-2005]
> 
> I think Steven effectively makes the point I have tried to make in a
> couple of previous submissions to this discussion. If someone who has
> been involved with the standardization process incorrectly assumes that
> the Verilog `&&' and `||' operators are short-circuiting (as they are in
> C, C++, Perl, Unix shells, Vera, and every other language I can think of
> that uses these symbols for logical conjunction and disjunction), how do
> we expect a user of the language to understand that the short-circuit
> evaluation is optional, and to write their code to take account of this
> semantic ambiguity?