[sv-bc] catching compiler directives at runtime.....

hello-


i wanted to ask if there is enough interest in the systemverilog
community to add the following, i am not aware if it is possible today,
i looked inside the LRM but couldn't find anything as such. but it
appears it could prove to be useful.

in RTL, we all use various compiler directives that are invoked during
compile/build time according to what suits our needs. i want to be able
to know, at runtime, if a certain compiler directive was used.


for example... suppose we have:


----------------------------------------------
module dff (q, d, clk);

parameter SIZE = 1;
output	[(SIZE - 1):0]  q;
input	[(SIZE - 1):0]  d;
input   clk;
reg	[(SIZE - 1):0]  q;
reg	[(SIZE - 1):0]  q_b;

`ifdef FF
	always @(posedge clk) q <= d;
`elsif LATCH
	always @(negedge clk) q_b <= d; //B-phase
	always @(d) if (clk==0) q_b <= d;

	always @(posedge clk) q <= q_b; //A-phase
	always @(q_b) if (clk==1) q <= q_b;
`else
	// structural modeling
`endif

endmodule
----------------------------------------------



during compile/build, say +define+LATCH was used. now, at runtime, i
would like to know if the binary/snapshot was generated with that
particular compiler directive. if all "+define+<...>"s are stored inside
a data structure within the binary/snapshot, then via a vpi routine, i
can access it and see what was used at the beginning of simulation.



inside a C code, i can have something like:


----------------------------------------------
char *str = (char *)NULL;
str = (char *)malloc(25*sizeof(char));

if ( (str = mc_scan_compilerdirective((const char *)"+define+LATCH"))
			!= (char *)NULL) )
  {
	// +define+LATCH was used
        // ... something similar to today's mc_scan_plusargs
  }
else if ( (str = mc_scan_compilerdirective((const char *)"+define+FF"))
			!= (char *)NULL) )
  {
	// +define+FF was used

  }
----------------------------------------------




thanks,
-nasim