RE: [sv-bc] Nested module questions

>From: "Bresticker, Shalom" <shalom.bresticker@intel.com>

>[Shalom] By data types, do you mean data objects? That actually covers
>most of the cases in old Verilog. In old Verilog, instead of the data
>object rule (declaration must precede use) being described as the
>exception, the task/function rule (declaration need not precede use) is
>considered the exception.
>
>In any case, it is not clear what rule applies in this case since the
>nested module declaration is within the same enclosing module where it
>is being used. Who says it is like tasks/functions and not like data
>objects?

Actually, there is no special "forward reference" rule for task/functions.
The appearance of such a rule falls out of the special rule that an
unresolved task/function name is treated as a hierarchical reference.
During the upward search to resolve the hierarchical reference, the
declaration in the local module is found first.  This is not a forward
reference; it is a hierarchical reference.

Since you cannot use a simple name for a module and do an upward
hierarchical search to resolve it to a nested module declared in your
parent, then that would not apply to a module declaration.  So the rule
that allows the appearance of forward references for tasks/functions does
not apply to modules.  So there is no precedent at all for allowing a
forward reference to a nested module declaration.

This is not a matter of what rule to apply.  There is only one rule, and
it requires declaration before use.

Steven Sharp
sharp@cadence.com