Re: [sv-bc] Interface modports vs. logic synthesis

Following up on http://www.eda-stds.org/sv-bc/hm/1690.html , in 20.4 of
IEEE Std 1800-2005 it says

 

      If a port connection specifies a modport list name in both the
module instance and module header declaration,

then the two modport list names shall be identical.

 

If there is either no modport specified in the port declaration of BOT
or a modport "different_mp" specified there, could the following be
legal?

 

   module TOP(IFC.mp port);

      BOT bot(port.different_mp);

   endmodule

 

I would have thought that such usage would be illegal, but don't see
anything in the LRM that says so.  I thought the intent was that once a
modport is wrapped around a reference to an interface instance, that
particular modporting stays with the reference, no matter how many
levels of hierarchy it gets passed through, with no possibility of
wrapping another more restrictive modport around it, or even rewrapping
the same modport around it, as in the following.

 

   module TOP(IFC.mp port);

      BOT bot(port.mp);

   endmodule

 

-- Brad