[sv-bc] Re: [sv-ec] Query regarding Macro substitution

I just noticed that Kausik sent this to the EC instead of the BC, which
might explain why there was no reply.  This falls more within the BC area.
I don't have the original email any more, just my reply to it.

The issue is what should happen if the `` characters appear as part of
an escaped identifier.  By normal Verilog rules, those would just be part
of the escaped identifier name.  For complete backward compatibility, SV
would have to give the same answer.  But that would mean that there is
no way to use the `` token-pasting operation in a macro to create an
escaped identifier.  That seems undesirable.  It may be worthwhile to
give up the backward compatibility in the unlikely case that someone has
used `` inside a Verilog escaped identifier, to get the ability to build
an escaped identifier with ``.

In case this is not clear, consider an example macro

`define foo(x) \abc[``x``]

In Verilog, `foo(0) would expand into \abc[``x``].  In other words,
the `` characters would just be treated as part of the escaped identifier,
and so would the x.  If SystemVerilog is fully backward compatible with
Verilog in this case, it would also have to expand into that.  But the
desired goal here is probably to get it to expand into \abc[0] instead.
It may be worthwile to lose the ability to create an escaped identifier
that contains `` in order to gain the ability to build escaped identifiers
with token-pasting.


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From: Steven Sharp <sharp@cadence.com>
Subject: Re: [sv-ec] Query regarding  Macro substitution 
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>From: "Kausik Datta" <kausikd@cal.interrasystems.com>

>LRM is not clear about how "``" will be interpreted within escaped
>identifier.

Well, the behavior is already defined in Verilog.  If SV is supposed
to be backward compatible with Verilog, then it should get the same
answer as Verilog (even though that may not be what would be preferred).

An escaped identifier includes all characters up until the next
white space, and that includes ` characters.  Verilog will treat
the `` in both of your examples as part of the escaped identifier.
If SV is backward compatible with Verilog, then it will also treat
them as part of the escaped identifier, not as a token pasting
operation.  Otherwise it would get a different result than Verilog
for existing code.  This means that you cannot use a `` to paste
together two tokens to create an escaped identifier (which could
be an inconvenient limitation).

From your example VCS output, it looks like they are trying to
treat the `` as a token pasting operation, but only inside a macro
that has an argument.  The logic is presumably that token pasting
is only really useful if you have a macro argument to paste onto
an identifier.  If there are no arguments, then it follows the rules.
Or maybe there isn't any logic, and this inconsistent behavior is
just an accident in their code.

Steven Sharp
sharp@cadence.com


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Steven Sharp
sharp@cadence.com