RE: [sv-bc] default port values

Yes, what I'm looking for is an ability to specify the default
expression to be assigned to an input port when the port is left
unconnected. It should not matter whether the port is a net or a
variable. A continuous assignment should be assumed.

 

Regarding the separate compilation, I'm not sure there should be a
problem as long as the default port value is properly specified in the
extern module declaration. 

 

Thanks for the answers so far,

Yulik.

 

________________________________

From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Rich, Dave
Sent: Friday, May 26, 2006 9:55 PM
To: Brad Pierce; sv-bc@server.eda.org
Cc: Patkin, Guy; Alsop, Thomas R
Subject: RE: [sv-bc] default port values

 

Some more background. 

 

Brad is describing a variable declaration assignment (VDA), which is an
initial default value, which is not the same as a default value for an
unconnected port. The problem is that a VDA is treated as a procedural
assignment, and an input port is treated as a continuous assignment, and
the two together are illegal.

 

What Yulik is asking for is for what looks like a VDA to be applied only
when there no connection on an input. This might be a problem for
separate compilation in synthesis because you wouldn't know if the
connection was going to be there or not.

 

For simulation and testbenches, it makes more sense to do something like
this. (But I am apposed to adding this now until we get through much
more errata).

 

Dave

 

 

________________________________

From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Brad Pierce
Sent: Thursday, May 25, 2006 6:49 AM
To: sv-bc@server.eda.org
Cc: Patkin, Guy; Alsop, Thomas R
Subject: Re: [sv-bc] default port values

 

The following is not an answer, but just some details about what is
currently allowed by the LRM.

 

In Verilog, you can initialize a variable output port just like any
other variable.  For example,

 

     module m #(parameter N=8)(input [N-1:0] i, output integer o =
f(N));

        ...

     endmodule

 

is the same as

 

     module m #(parameter N=8)(input [N-1:0] i, output integer o);

     initial o = f(N);

        ...

     endmodule

 

In Verilog, input ports cannot be variables.  In SystemVerilog they can
be, but they cannot be initialized.

 

See Footnote 25 of IEEE SV LRM --

 

      25) ...  It shall be illegal to initialize a port that is not a
variable output port.

 

-- Brad

 

 

________________________________

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Feldman, Yulik
Sent: Thursday, May 25, 2006 1:42 AM
To: sv-bc@eda.org
Cc: Patkin, Guy; Alsop, Thomas R
Subject: [sv-bc] default port values

 

Hi,

 

Is there a good reason why SV doesn't allow default values for ports,
like it allows default values for function/task arguments? Is this
feature missing because there was no request to add it to the language,
or because there was some legitimate reason not to add it? I remember
some old discussion about it, but I can't find the thread.

 

Thanks,

            Yulik.