RE: [sv-bc] Re: Ballot Issue 228: SystemVerilog should include 2-value net datatypes

Time.

 

 

The key issue is at foremost, is a 4-state wire really just 4 states
with associated strengths, or it a 120-states that get cast into
4-states when used in an expression.  

 

If the latter is true, then a 2-state wire would simply just cast the
120-states into a 2-state value when used in an expression. If the
former is true, then we've got serious problems dealing with multiple
drivers on a 2-state net and problems with collapsed nets.

 

Dave

 

 

________________________________

From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Brad Pierce
Sent: Wednesday, May 17, 2006 9:11 AM
To: sv-bc@server.eda.org
Subject: [sv-bc] Re: Ballot Issue 228: SystemVerilog should include
2-value net datatypes

 

As noted in http://eda.org/svdb/bug_view_page.php?bug_id=694 , the P1800
ballot issue 228, regarding the need for 2-state datatypes on nets, was
never fixed.

 

What are the key stumbling blocks that still need to be resolved for
this one?

 

-- Brad