[sv-bc] Queries related to pattern matching in case statement.

Hi,
I have some quaries related to pattern matching in case statement.

For pattern matchin case statement the rule is-
 case_statement ::= [ unique_priority ] case_keyword ( expression )
matches case_pattern_item { case_pattern_item } endcase

 case_keyword ::= case | casez | casex

 case_pattern_item ::= pattern [ &&& expression ] : statement_or_null
                       | default [ : ] statement_or_null

pattern ::=  . variable_identifier
           | .*
           | constant_expression
           | tagged member_identifier [ pattern ]
           | '{ pattern { , pattern } }
           | '{ member_identifier : pattern { , member_identifier :
pattern } }

and there is an example in SV LRM(IEE std 1800-2005 Standered for system
verilog) on page no -134
...
case (instr) matches
tagged Add '{reg2:.r2,regd:.rd,reg1:.r1} &&& (rd != 0): rf[rd] = rf[r1]
+ rf[r2];
tagged Jmp (tagged JmpU .a) : pc = pc + a;
tagged Jmp (tagged JmpC '{addr:.a,cc:.c}) : if (rf[c]) pc = a;
endcase
...

So my questions are -
 a) in the ablove rules there is no '(' or ')' used with the pattern.So
is this example is valid one?
b) If it is valid one then whether that '(' and ')' will be used  from
the 2nd recursivly used pattern?
c) is this exmaple is valid or not-
case (instr) matches
tagged Add '{reg2:.r2,regd:.rd,reg1:.r1} &&& (rd != 0): rf[rd] = rf[r1]
+ rf[r2];
(tagged Jmp (tagged JmpU .a) ): pc = pc + a;
(tagged Jmp  tagged JmpC '{addr:.a,cc:.c}) : if (rf[c]) pc = a;
endcase
Thanks and regards.
Surya