Re: [sv-bc] Final blocks in packages

Brad Pierce wrote:

> Gord,
> 
> That seems reasonable to me, because of the analogy with an
> initialization in a module declaration, which wouldn't happen unless the
> module were instantiated, but is there any textual support for it in the
> current LRM?

Not really; the closest would be 19.2:

    ... in the same way as variables declared in a compilation unit or module.

The LRM (to me) clearly considers a package scope to be a "atomic"
thing; visibility of items within the scope are controlled by
import but the "package" itself is never discussed as anything
other than a "scope".  Since Verilog does not in any other
circumstance allow an implementation to skip behavior within
a scope that is part of the design, I don't see why you would
expect anything different here.

Treating packages differently in terms of observable effects would
be a significant change and would require explicit language to
allow such an interpretation rather than the opposite.

Claiming that a package is not part of the design if it is referenced
but does not have any names imported from it is problematic since
the package *WAS* considered part of the design during compilation
(since its declarations were visible for import).  Such an interpretation
would also mean that behavior could change due to the simple import
of a type (or similar) from a package that was previously imported
but unused.  Do we really want the kind of behavior sensitivity in
designs?

As a similar question -- if the only imported name reference was
in an unelaborated generate block, would you want to consider
the package imported?

    module m;
      if (0) begin
        pkg::T a;
      end
    endmodule


A similar issue arises with "top module" determination.  1364 resolves
that issue by saying that a module is a a "top module" if there
is no *instantiation statement*.  This used to read "if there is
no instantiation" but that leads to huge problems.  I think the
same applies to packages and so we should consider any *possible*
use as a use.

Gord.


> 
>>as far as I am concerned, if a package
>>is used in the design (referenced in an import or included via
>>some other vendor mechanism) then all of its initializations
>>occur.  A reference to the package is sufficient -- no actual
>>import needs to occur.
> 
> 
> -- Brad
> 
> 
> 

-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com