RE: [sv-bc] In-line variable initialization

Regardless, the original question was, where does the text of the LRM,
as opposed to the BNF, say that variable declarations can have
initializers in begin/end and fork/end blocks, tasks, functions, or
$unit? In contrast to Verilog, where they can have initializers only in
module level declarations.

Steven suggested 6.4 and 6.6.

The only thing I found is that 6.4 says, "A variable can be declared
with an initializer." That statement is unconditional, so technically it
covers all the cases (assuming that a variable declaration EVERYWHERE
really can have an initializer). However, since this differs from
Verilog, it needs to be stated explicitly.

Shalom


> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Brad Pierce
> Sent: Saturday, April 22, 2006 8:37 PM
> To: sv-bc@server.eda.org
> Subject: Re: [sv-bc] In-line variable initialization
> 
> Then let's help the users and put a restriction back in saying that an
> in-line variable initialization shall not be used in the declaration
of
> a static variable unless the static lifetime is explicitly indicated
> with the 'static' keyword.