>From: "R.S.Nikhil" <nikhil@bluespec.com> > >I agree fully with the sentiment, but I thought >that this "feature" of optional parentheses was for backward >compatibility with Verilog. No. Functions without arguments are illegal in Verilog (perhaps as an attempt to discourage "impure" functions). There is no backward compatibility issue with Verilog here. There are consistency arguments that can be made. Verilog tasks calls with no arguments omit the parens, and calls to the few system functions that have no arguments also omit the parens. But neither of these cases is syntactically ambiguous. We could also allow optional empty parens in these cases, if desired for greater consistency in syntax. >Also, some people have argued that when b and c are object >members (i.e., m.b+m.c) they want to hide the fact whether >b and c are actually variables or functions. (Personally >I'm not sympathetic to that argument). Neither am I. As Gord has pointed out, the object oriented languages in most common use don't allow this, and it doesn't seem to have created a problem. Similar arguments in VHDL led to syntactic ambiguity between function calls and array indexing, which has caused far more harm than benefit. As time goes on, we find more problems being caused by allowing this syntactic ambiguity. The most recent is Gord's email about system tasks that accept scopes as arguments, and the inability to distinguish whether a function name in that context is intended as a scope or a function call. We should stop this before it gets any worse. Steven Sharp sharp@cadence.comReceived on Mon Apr 17 11:42:11 2006
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