RE: [sv-bc] Referring into generate scope via interface port

Brad,

 

Did you ever get an answer to this?

 

Shalom

 

________________________________

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Brad
Pierce
Sent: Tuesday, February 28, 2006 8:42 AM
To: sv-bc@eda.org
Subject: [sv-bc] Referring into generate scope via interface port

 

When an interface is passed through a module port without using a
modport, is it legal to refer into the generate scopes of the interface?

For example, if GEN[5] is a generate scope in the interface and 'sig' is
a wire declared within that scope, can I use an interface port 'ifc' of
a module to get at that wire?

     assign ifc.GEN[5].sig = 1'b0;

Apparently, I cannot list generated signals in a modport without using
the modport expression syntax. According to Syntax 20-1 the following is
not legal

    modport mp(input GEN.sig);

and I am forced to do

    modport mp(input .\GEN[5].sig (GEN[5].sig));

Is the BNF correct, or is it just trying to prevent passing out
hierarchical references or fields of a struct without a modport
expression, while forgetting about the possibility of generated signals?

If the BNF is correct, and I pass a modport instead of a naked
interface, then there's suddenly no way to say

   assign ifc.GEN[5].sig = 1'b0;

and I am forced to use modport expressions

   assign ifc.\GEN[5].sig = 1'b0;

-- Brad