RE: [sv-bc] Question on support of a construct for Verilog - 2001

>It is correct that @(array_name) does not work in Verilog, as the
>language syntax requires that the sensitivity list be a list of
>variables. A specific array element is a variable whereas the entire
>array is a group of variables, which is not the same thing.

Minor correction:
The syntax requires that the event control contain *expressions*.
An event is defined by whether that expression changes value (you
could view this as using the case equality operator to compare the
old and new values of the expression).  An entire array is not an
expression in Verilog.


>In @*, a strict interpretation of the language might give an
>implementation which also does not allow it. However, in practice, tool
>vendors have implemented @* by creating an implicit sensitivity list
>with all the elements of the array.

Note that such an implementation may not involve actually building
a sensitivity list with all the elements in it.  It may involve
something much like waiting on the entire array.  But that doesn't
mean it is a good idea to allow an entire array to be specified
explicitly in an event control.

An implicit event control created with @* will always consist only
of identifiers.  In this special case, a wait on an entire array
can be done efficiently.  But an explicit event control does not
have this restriction, and could become extremely inefficient if
entire arrays were allowed.


>SystemVerilog has defined an improvement on always @* called always_comb
>which explicitly takes care of the array case, along with other
>improvements.

Actually, it fails to define the meaning of the "expansion" of the
longest static prefix, so it doesn't really define the array case
properly.


>With respect to whether the next version of the SystemVerilog standard
>should allow you to list an array name in an explicit sensitivity list,
>I will try to check whether such an enhancement request already exists.
>If not, I will file such a request, though there is no commitment that
>such a request will be fulfilled.

Note that in SystemVerilog, an aggregate such as an array is a valid
expression, with operators such as equality defined.  So an array would
be valid in an event control, except that the LRM explicitly disallows it.
This is apparently an attempt to avoid inefficiency.

Unfortunately, always_comb has defined the implicit sensitivity list
with this "longest static prefix" rule.  This means that the list does
not necessarily consist only of identifiers, and could contain large
aggregates, so its implementation could be very inefficient.
 

Steven Sharp
sharp@cadence.com