RE: [sv-bc] reg vs. logic

From: Arturo Salz <Arturo.Salz_at_.....>
Date: Mon Mar 06 2006 - 10:56:20 PST
But, I believe that currently reg and logic are not the same.

 

Both reg and logic denote a 1-bit, 4-state datatype. However, logic is
only a type whereas reg is both a type and a variable. In that sense,
only a reg, which is a variable --- thus holds the previous value of an
output --- should be used in a UDP.

 

            Arturo

 

-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Michael (Mac) McNamara
Sent: Monday, March 06, 2006 9:58 AM
To: Rich, Dave; Bresticker, Shalom; sv-bc@eda.org
Subject: RE: [sv-bc] reg vs. logic

 

Isn't this just the ancient sequential UDP syntax, which holds the
previous value of the output in a 1364 reg, so that the new value can be
specified in the table as a function of the inputs, and the registered
current output?

 

I do not view this as an arbitrary reuse of a keyword.  This reg has all
of the same behavior of any other declaration of a module with a
registered output.  It would have been less useful if different syntax
were used. 

 

As both output reg declarations are the same, then because elsewhere we
say that "reg" and "logic" are synonyms, then logically it should follow
that one should be able to use "logic" here.

 

( I will enclose my gripe about introducing multiple ways to specify the
same thing, while also using up a useful five letter word in
parenthesis).

 

 

 -----Original Message-----

From:   Rich, Dave [mailto:Dave_Rich@mentor.com]

Sent:    Mon Mar 06 08:23:47 2006

To:       Bresticker, Shalom; sv-bc@eda.org

Subject:            RE: [sv-bc] reg vs. logic

 

One could argue that the 'reg' keyword is being re-used here and is not

the same a 'reg' variable.

 

 

 

________________________________

 

From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of

Bresticker, Shalom

Sent: Monday, March 06, 2006 6:58 AM

To: sv-bc@eda.org

Subject: [sv-bc] reg vs. logic

 

 

 

A.5.2 shows the following BNFs:

 

 

 

udp_output_declaration ::=

 

      { attribute_instance } output port_identifier

 

    | { attribute_instance } output reg port_identifier [ =

constant_expression ]

 

 

 

udp_reg_declaration ::= { attribute_instance } reg variable_identifier

 

 

 

 

 

Are these exceptions to the rules that reg and logic are the same, or

oversights in the BNF?

 

 

 

Shalom

 

 

 

 

 

Shalom Bresticker

 

Intel Jerusalem LAD DA

 

+972 2 589-6852

 

+972 54 721-1033

 

I don't represent Intel 

 

 

 

 
Received on Mon Mar 6 10:56:30 2006

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