RE: [sv-bc] Aggregate / struct - 2 questions

> Two aggregate / struct questions below.
[from Cliff Cummings]

> (1)     The init function takes a pkt_s structure as an input. When I 
> make the following assignment, one SystemVerilog simulator passes 
> while another reports an error due to the apostrophe in from of the {

As others have pointed out, this is 3.1a legacy syntax supported
by one simulator that doesn't yet support assignment patterns.
I think you'll find that the same simulator also supports 
the 3.1a notion of $root, too :-)

> Is there some way to unpack the struct (almost like aggregate 
> de-assignment) so that the display command could be written 
> something like:
> 
> $display("dst=%h src=%h data=%h crc=%h", pkt1);

I personally don't think this is a very good idea.

If the struct were packed, as is likely for synthesis, then
you couldn't reasonably do this (because the packed struct
also has a perfectly good integer value when taken as a whole).
This could lead to all sorts of hideous ambiguity; how about
this... (p2 is of the same type as pkt1):

$display(
   "pkt1=%h, p2.dst=%h p2.src=%h p2.data=%h p2.crc=%h", 
       pkt1, p2);

How could $display work out which %h is associated with what?

For simulation only, you could use a class instead, and then
the class could provide its own to-string method - psdisplay()
in VMM-speak.  And indeed, since we now have a full-fledged 
string data type, it's easy to provide a to-string function
for any data type.

I sometimes wonder whether there is any utility at all in
unpacked structs.  They make little sense for synthesis, and
for simulation it's surely better to use a class; the class can
then have a pack method that converts the appropriate parts of
its content into a packed struct suitable for injection into
an RTL model.
-- 
Jonathan Bromley, Consultant

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